1. Field of the Invention
The present invention relates to digital systems, and, more particularly to a circuit and method which substantially reduces the occurrence of metastability during dam transfer between a first digital subsystem operating at a first clock frequency and a second digital subsystem operating at a second clock frequency.
2. Description of the Prior Art
A synchronizer circuit is used in digital systems to manage data transfer between two subsystems, each operating at a different clock frequency. Referring to FIG. 1, a digital system is shown. The digital system 10 includes a first subsystem 12 operating at a first clock frequency f.sub.1 (CLK f.sub.1), a second subsystem 14 operating at a second frequency f.sub.2, (CLK f.sub.2) and a synchronizer circuit 16. The synchronizer circuit 16 includes a first master synchronizer cell 18a, a first slave synchronizer cell 18b, a clock divider 20, and an inverter 22 for handling data transfer between the first subsystem 12 to the second subsystem 14. The synchronizer 16 also includes a second master synchronizer cell 18c and a second slave synchronizer cell 18d, a clock multiplier circuit 24, and a second inverter 26.
The synchronizer circuit 16 is responsible for handling data transfer from the first digital subsystem 12 to the second digital subsystem 14, and vice versa. During data transfer from the first subsystem 12 to the second subsystem 14, the first subsystem 12 places data on its node Dout. The clock divider 20 receives CLK f.sub.1 from the first subsystem 12 and divides it with a denominator so that the output frequency of the clock divider 20 substantially equals CLK f.sub.2 of the second subsystem 14. The inverter 22 inverts the signal CLK f.sub.2 creating signal CLK f.sub.2 . Accordingly, the rising edge of CLK f.sub.2 coincides with the falling edge of CLK f.sub.2 and visa versa. The master synchronizer cell 18a latches the data present at its node Din and provides that data to its output at nodes Q and Q during the period of CLK f.sub.2. The slave synchronizer cell 18b latches and provides the data at nodes Q and Q to node Din of the second digital subsystem 14 when the signal CLK f.sub.2 transitions high. Since the data transfer operation is essentially the same in both directions, a similar description of the data transfer from the second digital subsystem 14 to the first digital subsystem 12 is not provided. Assuming the frequency of CLK f.sub.1 is greater than of CLK f.sub.2, it should be noted that the clock multiplier 24 is used in place of the clock divider 20 for data transfer from the second subsystem 14 to the first subsystem 12.
The synchronizer cells 18a, 18b, and 18d are essentially the same. Accordingly, only synchronizer cell 18a is described.
Referring to FIG. 2, a circuit diagram of the synchronizer cells 18a according to the prior art is shown. The circuit diagram of the cell 18a includes an N channel transistor 30, N channel transistor 32, N channel transistor 34, N channel transistor 36, inverter 38 and inverter 40. Inverter 38 includes N channel transistor 42 and P channel transistor 44. Inverter 40 includes N channel transistor 46 and P channel transistor 48. The gate of transistor 34 is coupled to Din, and the gate of transistor 30 is coupled to CLK f.sub.2. The source and drain of transistor 30 and transistor 34 are coupled in series between node Q and ground. The gate of transistor 32 is coupled to CLK f.sub.2, and the gate of transistor 36 is coupled to Din. The source and drain of transistor 32 and transistor 36 are coupled between node Q and ground. The gates of transistor 42 and transistor 44 of inverter 38 are coupled to node Q, and the output of the inverter 38 is coupled to node Q. The gates of transistor 46 and transistor 48 of inverter 40 are coupled to node Q, and the output node of the inverter 40 is coupled to node Q.
During operation, the first subsystem 12 initiates a data transition on its node Dout when transferring data to the second subsystem 14. The data transition is applied to node Din of the first master synchronizer 18a. If the transition at Din of the synchronizer cell 18a coincides with a clock period of CLK f.sub.2, transistor 34 and transistor 30 respectively turn on, pulling down node Q. On the complementary side of the circuit, transistor 36 turns off as Din transitions low. As a result, node Q is driven high. The inverter 38 and the inverter 40 regeneratively drive one another, causing node Q to be pulled up and node Q to be pulled down. With the rising edge of CLK f.sub.2 , which corresponds to the falling edge of CLK f.sub.2, the logic potentials at node Q and node Q are latched by the slave synchronizer cell 18b and the data is provided to the second subsystem 14 in the same manner as described above.
One problem associated with the data transfer operation described above is that the digital system 16 is susceptible to metastability because data applied at node Din of the synchronizer cell 18a is asynchronous with respect to the clock signal CLK f.sub.2. More specifically, metastability typically occurs when CLK f.sub.2 is transitioning low, while Din is transitioning high. Under these circumstances, transistor 34 turns on, as transistor 30 begins to turn off. On the complementary side of the circuit, both transistor 32 and transistor 36 are turning off as CLK f.sub.2 and Din transition low respectively. Node Q may consequently be pulled to an intermediate voltage between Vcc and ground during the set up time of inverter 38, causing the regeneratively driven inverters 38 and 40 to possibly enter an "equilibrium" state. As a result, node Q and Q may become "trapped" at a metastability voltage, somewhere between Vcc and ground. This phenomena occurs because of the symmetrical design of the inverter 38 and inverter 40. Transistors 42 and 44 of inverter 38 and transistors 46 and 48 of inverter 40 all conduct equally when node Q and Q are at the metastability voltage. Nodes Q and Q may stay in the metastability condition indefinitely, until noise or some other factor causes the inverter 38 and inverter 40 to trip in one direction.
Dobberpuhl, in the article entitled "The Design and Analysis of VLSI Circuits", Addison Welsey, 1985, teaches a formula for calculating the average mean time before metastability failure (MTBF). The equation provides: ##EQU1##
Based on Dobberpurl's observations, the key to increasing MTBF is to maximize the value T.sub.au. This may be accomplished by increasing the gain bandwidth of the transistors 42, 44, 46 and 48 of inverters 38 and 40 respectively. The gain bandwidth is proportional to gm/C where gm is the gain of the individual transistors 42, 44, 46 and 48 and C is the capacitance at nodes Q and Q of the cell 18.
The gain (gm) of the transistors 42, 44, 46 and 48 may be increased by enlarging the gate width or size these devices. The drawback with this approach, however, is that the larger the transistors, the greater the capacitance (C) at nodes Q and Q. The advantages of the gain increase are therefore mitigated by the additional capacitance. Further, the larger transistors may also be unacceptable on modem VLSI chip designs because they may occupy too much space on the die.
Another problem with the prior art synchronizer cell 18 is that the pull down of nodes Q and Q occurs through the source and drain of the same switching devices used to control the potential at these nodes, namely transistors 30 and 34 and transistors 32 and 36 respectively. This arrangement is undesirable because the speed at which these nodes are pulled down is dependent on the switching characteristics of these transistors. Since these transistors 30 and 34 are typically relatively small MOSFET devices, their switching speed is relatively slow and their pull down capability is relatively week. Both these characteristics tend to increase the probability of metastability because it takes a longer period of time for the nodes Q and Q to switch from rail to rail, increasing the likelihood the nodes will get "stuck" between V.sub.cc and ground.